The common format for digital signal data transmission between remote stations is by serial bit transmission over a single wire. The signal information is transmitted in serial bit frames, each including a selected N number of serial bits preceded by a first START bit signaling the beginning of the frame. The serial bits are transmitted at a selected line frequency established by the transmitting station. When the transmitting station clock signal is not transmitted to the receiving station the data transmission is asynchronous.
The receiving station signal data systems typically operate on parallel formatted data so that the received serial data must first be reassembled in parallel. The serial-to-parallel conversion is done with shift registers. The received serial data bits are strobed serially in each frame into the shift register at a sampling frequency established by a local oscillator. The strobing in of the data must occur at the same rate as the line frequency to avoid losing data bits, so that the sampling frequency must be equal to and phase synchronized with the line frequency.
The receiver local oscillator is phase synched to the incoming line frequency by detecting the presence of each frame's START bit. This is provided by detecting the logic state transition associated with each START bit. In the prior art Universal Asynchronous Receiver/Transmitter (UART) the START bit transition is evidenced by detection of the leading edge with a higher than line frequency clock, e.g. a "16 X clock" which samples the received data line at 16 times the line frequency. The leading edge is located to within one clock sample interval at the point at which the samples change state. Maintenance of the logic state change for a selected time interval (e.g. one half the bit time interval for return to zero (RZ) signals) assumes a valid START bit. Thereafter a counter is enabled which counts down the higher (16 X) clock signal to the line frequency rate to produce a sampling clock frequency which samples the incoming data once per bit cell. The phase of the divided down sample clock signal is adjusted, based on the START bit edge location to provide sampling of each data bit more or less at the center of its information state. For RZ signal formats this occurs at a quarter bit cell time.
With a 16 X clock the START bit edge location error is one in 16, or 6.3 percent. The error may be made smaller by using a higher frequency, e.g. 32 or 64 X. Obviously higher edge sampling rates require faster edge detection circuitry. For incoming line frequencies on the order of 10 MHZ a 16 X clock equals 160 MHZ; a 32 X clock twice that frequency, and so on. However, for optical data line frequencies (e.g. high frequencies typically on the order of 50 MHZ or more) it is impractical to use line receivers employing higher than line frequency clock interfaces.